Present flash technologies have encountered significant challenges for scaling such as scaling of program/erase (P/E) voltage, speed, reliability, and high densities with non-volatile data. Attempts to solve such issues have included employing RRAMs due to their scalability, highly competitive speed, endurance, and retention properties. However, RRAMs suffer from poor resistance uniformity, smaller memory margin, and poor performance back-end-of-line (BEOL) cell selectors.
The poor resistance distribution has been attributed to more filament current paths in a planar device, which leads to increased variations between set and reset, since some cells give more current paths than others. Single transistor single resistor (1T1R) RRAMs, which are desirably bipolar and have a high access current, also have a large cell size of 8F2 or higher, are not easily scalable, and have a planar memory margin. Single diode single resistor (1D1R) RRAMs, on the other hand, have a smaller cell size of 4F2 or higher, and are easily scalable, but are unipolar, have a low access current, and have a planar memory margin. In addition, 1D1R RRAMs employ metal oxide diodes or organic diodes, which are compatible with back-end-of-line (BEOL) processes because of processing temperatures less than 400° C. However, the diodes of such materials are not tunable, have inferior diode performance (i.e., low forward current due to large band-gap), which leads to larger cell area and a high Vdd of 3 to 4.5 V, which is not compatible with low Vdd technology.
Attempts to improve the resistance distribution include a plug bottom electrode instead of a planar bottom electrode to limit the number of filament current paths for memory cells. The plug bottom electrode improves reset current distribution and memory margin by a factor of about four. However, RRAMs using bottom plugs are not easily scalable.
A need therefore exists for methodology enabling fabrication of easily scalable RRAMs which have a small cell size, bipolar access, and improved resistance distribution and memory margin, and the resulting product.